Test Analysis & Equipment Utilization

Reliability Test Service

Life Test

A typical time distribution for semiconductor component failures is depicted by the bathtub curve as in figure. The curve has three distinct regions: a rapidly decreasing “infant mortality” portion; a stable, useful life portion (where the failure rate continues to decrease or is essentially constant); and a period of increasing failure rate representing the onset of wear-out. Infant mortality and useful life failures are caused by defects introduced during the manufacturing process. Many of these component defects can be removed by effective reliability screens. Early life fails are defect-induced component failures during board or system assembly processes, or during initial customer use. Product ELFR data typically includes several different failure mechanisms, which may contribute failures differently as a function of voltage, temperature and time. It is important to apply the correct voltage and temperature acceleration factors for each individual failure mechanism when projecting reliability performance to actual use conditions. QRT not only performs early life failure rate (ELFR) testing accurately but also provides failure analysis services. Early life failure rate calculation procedures may change according to failure distribution, which is represented by FIT or PPM. While early life failure rates are calculated with activation energy (Ea) and γV (Experimentally determined electric field constant/Thickness of stressed dielectric) provide by customers, we draw a conclusion by referring to JEDEC or presuming specific values.
Early LifeFailure Rate Test

Summary of ELFR

Temperature Bias Duration Sample Size
Tj ≥ 125 °C Maximum Operating Voltage 48 ≤ t ≤ 168 hrs Refer to JESD47

* Varies from at least 229 to 115,153 according to the desired FPM level.

JEDEC testing is intended to calculate early life failure rates but AEC testing is a pass/fail test.
Grade 0: 48 hours at 150 °C or 24 hours at 175 °C sample Size : 3Lots (800 units/lot)
Grade 1: 48 hours at 125 °C or 24 hours at 150 °C
Grade 2: 48 hours at 105 °C or 24 hours at 125 °C
Grade 3: 48 hours at 85 °C or 24 hours at 105 °C
Grade 4: 48 hours at 70 °C or 24 hours at 90 °C

* Conduct a test under the above one or more conditions. The parts shall be electrically tested within 48 hours after completion of tests. If the test results in 0, then it acquires specific corresponding grade.

Reference Documents

  • JESD22-A108 “Temperature, Bias and Operating Life”
  • AEC-Q100-008 “Early Life Failure Rate”

Unlike burn-in inducing early life failures, HTOL is a testing item intended to test how long life a product will have under the use condition and focuses on wear-out failure.
Accordingly, life tests shall be conducted for an enough long period of time so that they may not be affected by what is introduced during early life failure period or infant mortality period.
Test duration may increase or decrease according to ambient temperature.
Unless otherwise specified, all intermediate and end-point electrical tests must be performed on the parts within 96 hours after their removal from the specified burn-in conditions.
If not specified, an intermediate electrical testing shall be performed after 168 (+72,-0) hours and after 504 (+168,-0) hours Since HTOL is simply long-term burn-in, it is accomplished by utilizing any burn-in oven capable of operating continuously over long durations.
Failure mechanisms accelerated by HTOL include Time-Dependent Dielectric Breakdown (TDDB), electromigration, hot carrier effects, charge effects, mobile ionic contamination, etc.

Summary of HTOL

Temperature Bias Duration
Tj ≥ 125 °C Maximum Operating Voltage 1000 hours

Reference Documents

  • JESD22-A108 “Temperature, Bias and Operating Life”
HTOL Equipment

The Low Temperature Operating Life (LTOL) test is a test performed to determine the reliability of devices under low temperature conditions over an extended period of time.
This test shall be performed at a specified low temperature for a specified amount of time after bias is authorized as specified in test samples.
The LTOL test is basically just the low temperature equivalent of the HTOL test.
In fact, both tests are documented by JEDEC in a single standards spec, JEDEC-JESD22-A108. As in HTOL, there are several requirements when powering up a device during LTOL.
The device must not be overstressed nor should it go to thermal runaway. The datasheet limits of the manufacturer must not be exceeded.
Testing conditions shall be continuously applied for all amounts of time except intermediate tests.
Unless otherwise specified, the ambient temperature for LTOL test shall not exceed the maximum limit of 40 ℃.
Intermediate tests must be performed within 96 hours after the bias to the device has been removed.
A device is considered an LTOL failure if it fails to meet the applicable procurement specification. The LTOL test is usually performed to evaluate hot carrier effects, which are accelerated by high voltages and low temperatures.

Summary of LTOL

Temperature Bias Duration Sample Size
Tj ≤ 50 °C (Maximum Ta ≤ -40 °C) Maximum Operating Voltage 1000 hours 1Lots / 32units

Reference Documents

  • JESD22-A108 “Temperature, Bias and Operating Life”
LTOL Equipment
A non-volatile memory endurance & retention test consists of endurance test and data retention test. Repetitive write and erase pulses are applied to the memory as many times as specified in endurance test specifications. If it passes the test, retention tests are performed after total samples are half divided. For endurance tests, write-in patterns and write/ erase portion should be designated by designer or reliability engineers. Retention test may vary slightly according to specification. While HTSL and LTOL JEDEC are used under JEDEC, HTOL and HTSL are used under AEC.
Endurance Cycling Test
Data Retention Test
Option 1: Tj = 100 °C Option 2: Tj = 125 °C Ta = 25 °C
3 Lots / 39 units 3 Lots / 38 units
Cycles per NVCE(≥55 °C) / 96 and 1000 hrs / 0 Fail Cycles per NVCE(≥55 °C) / 10 and 100 hrs / 0 Fail Cycles per NVCE(25 °C) / 500 hrs / 0 Fail

Reference Documents

  • JESD22-A117 “Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Stress Test”
  • AEC-A100-005 ”Non-Volatile Memory Program/Erase Endurance, Data Retention, and Operational Life Test”